A liquid crystal display device controls a light transmittance of liquid crystal cells in accordance with a video signal, thereby displaying a picture.
An active matrix type liquid crystal display device is advantageous in realizing a motion picture because it is possible to actively control a switching device. A thin film transistor (TFT) is used as a switching device used in the active matrix type liquid crystal display device.
As shown in FIG. 1, The liquid crystal display device includes a liquid crystal display panel 2 where a plurality of data lines 5 and a plurality of gate lines 6 cross each other and of TFTs are respectively formed at the crossing parts thereof for driving liquid crystal cells; a data driver 3 for supplying data to the data lines 5; a gate driver 4 for supplying a scan pulse to the gate lines 6; and a timing controller 1 for controlling the data driver 3 and the gate driver 4.
The liquid crystal display panel 2 has a liquid crystal injected between two glass substrates, and the data lines 5 and the gate lines 6 perpendicularly cross each other on a lower glass substrate. The TFT formed at the crossing part of the data line 5 and the gate line 6 supplies the data from the data line 5 to the liquid crystal cell in response to the scan pulse from the gate line 6. A gate electrode of the TFT is connected to the gate line 6 and a source electrode is connected to the data line 5. A drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc. Further, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 2 for sustaining a voltage of the liquid crystal cell.
The timing controller 1 receives digital video which may be in the red-green-blue (RGB) data format, a horizontal synchronization signal H, a vertical synchronization signal V, and a clock signal CLK. The timing controller 1 generates a gate control signal GDC for controlling the gate driver 4 and a data control signal DDC for controlling the data driver 3. Further, the timing controller 1 supplies the RGB data to the data driver 3. The data control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE, and is supplied to the data driver 3. The gate control signal GDC includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, and is supplied to the gate driver 4.
The gate driver 4 includes a shift register which sequentially generates the scan pulse in response to the gate control signal GDC from the timing controller 1; a level shifter for shifting a swing width of the scan pulse to a level which is suitable for driving the liquid crystal cell Clc; and an output buffer. The gate driver 4 supplies the scan pulse to the gate line 6, thereby turning on the TFTs connected to the gate line 6 to select the liquid crystal cells Clc of one horizontal line to which a pixel voltage of the data, for example, an analog gamma compensation voltage, is to be supplied. The data generated by the data driver 3 are supplied to the liquid crystal cells Clc of the horizontal line which is selected by scan pulse.
The data driver 3 supplies the data to the data lines 5 in response to the data drive control signal DDC supplied from the timing controller 1. The data driver 3 samples the digital data RGB from the timing controller 1, latches the data, and then converts the data to into an analog gamma voltage. The data driver 3 is realized as a plurality of data integrated circuits (IC) 3a having the configuration as in FIG. 2.
Each of the data IC 3a, as shown in FIG. 2, includes a data register 21 to which the digital data RGB is inputted from the timing controller 1; a shift register 22 for generating a sampling clock; a first latch 23, a second latch 24, a digital/analog converter (DAC)25 and an output circuit 26 which are connected between the shift register 22 and k data lines DL1 to DLk; and a gamma voltage supplier 27 connected between a gamma reference voltage generator and the DAC 25.
The data register 21 supplies the digital data RGB from the timing controller 1 to the first latch 23. The shift register 22 shifts the source start pulse SSP from the timing controller 1 in accordance with the source sampling clock SSC to generate a sampling signal. Further, the shift register 22 shifts the source start pulse SSP to transmit a carry signal CAR to the shift register 22 of the next stage. The first latch 23 sequentially samples the digital data RGB from the data register 21 in response to the sampling signal sequentially inputted from the shift register 22. The second latch 24 latches the data inputted from the first latch 23, and then simultaneously outputs the latched data in response to the source output enable signal SOE from the timing controller 1. The DAC 25 converts the data from the second latch 24 into gamma voltages using reference voltages DGH and DGL from the gamma voltage suppler 27. The gamma voltages DGH and DGL are analog voltages corresponding to the gray levels of the digital input data. The output circuit 26 includes an output buffer connected to each of the data lines. The gamma voltage supplier 27 subdivides the gamma reference voltages GH and GL to supply the gamma voltage corresponding to each gray level to the DAC 25.
The data IC 3a has its load increased, driving frequency and the amount of generated heat is increased as liquid crystal display devices have increased in size and fidelity. Due to the heat generated by the data IC 3a, the reliability of the data IC 3a is decreases. A major source of the generation of heat in the data IC 3a is the output buffer 26a, shown in FIG. 3. The data IC 3a generates the heat by power consumption due to currents Isource and Isink flowing through internal resistive components of the output buffer 26a. 
In order to improve the charging characteristics of the liquid crystal cell and to reduce power consumption, the data IC is being realized by a charge share method where the data voltage is supplied to each data line in a state where the data lines are disconnected after the adjacent data lines are connected to pre-charge the data line with a charge share voltage generated due to a charge share between the data lines, or by a pre-charge method where the data voltage is supplied to the data line after the data line is pre-charged with a pre-charge voltage being a pre-set external voltage.
In the charge share method, as shown in FIG. 4, currents flow in the output buffer 26a in an output buffer driving section where it is changed from a charge share voltage Vshare to a data voltage, and thus the heat generation and the power consumption are increased. In the pre-charge method, as shown in FIG. 5, a voltage of a driving area of the output buffer 26a is reduced due to the pre-charge voltage +Vpre or −Vpre supplied in advance as a relatively high external voltage when the data voltage is high, e.g., a white voltage in a normally black sequence, thereby decreasing the temperature of the data IC 3a. But, the temperature of the data IC 3a is increased and the power consumption is rapidly increased in the pre-charge driving area 51, 52 of the low data voltage due to the pre-charge voltage +Vpre or −Vpre supplied from the outside, where it is high, for data voltage which is a mean value or less.